Monday, March 19, 2018

Negative Testing in functional verification!!!

Imagine someone on an important call and the mobile device reboots suddenly! The call was to inform that the devices installed at the smart home seems to be behaving erratically with only elderly parents & kids to provide any further details. On booting up, the smartphone flashes that there has been a security breach and data privacy has been compromised. Amidst this chaos, the car’s cruise control didn’t respond to pressing of the pedals!!! Whew!!!.... nothing but one of the worst nightmares in the age of technology we live in! But what if some of it could be true someday? What if the user has little or no idea about that technology?

The mobile revolution has enabled a common man to access technology and use it for different applications. The data from Internet world statistics suggest that internet adoption worldwide has increased from 0.4% of world population in 1995 to 54.4% in 2017. Related data also indicate that a sizable portion of the users are aged & illiterate. The ease of use has potentially driven this adoption further with the basic assumption that devices would be functioning correctly 24x7 even if used incorrectly out of ignorance. The same assumptions are seamlessly getting extended to safety critical domains such as Medical & Auto introducing several unknown risks for the user.

So how does this impact the way we verify our designs?

Traditionally, verification is assumed to be ensuring that the RTL is an exact representation of the specifications. Given that the state space based on the design elements is so very huge, a targeted verification approach covering positive verification has been in practice all throughout. Here, Proof of no bug is assumed to be equal to No proof of bug! The only traces of anything beyond this approach include –

- Introducing asynchronous reset during the test execution to check that the design boots up correctly again.
- Introducing stimulus triggering exceptions in the design.
- Simulating architecture or design deadlock scenarios.
- Playing around with key signals per clock for low power scenarios and reviewing the corresponding design response.

But as we move forward with security and safety becoming key requirements of the design, is this good enough? There is a clear need to redefine the existing approach and bring Negative testing to mainstream! Negative testing ensures that the design can gracefully handle invalid inputs, unexpected user behavior, potential security threats or defects such as structural faults introduced while the device is operational. Amidst shrinking design schedules, negative testing really requires creative thinking coupled with focused effort. 

To start with, it is important to question the assumptions used while defining the verification plan for the design. Validating those assumptions itself can lead to a set of scenarios to be verified under this category. Next, review the constraints applied while generating stimulus to list out potential illegal inputs of interest. Caution should be taken in defining this list as the state space would be large. Reviewing it in the context (Context Aware Verification) of end application would surely help in narrowing down this illegal stimulus set. Further to this, faults need to be injected at critical points inside the DUT using EDA tools or innovative testbench techniques. This is important for safety critical applications where the design needs to respond to random faults and exit properly while notifying about the fault or even correct it. Of course not to forget that appropriate coverage needs to be applied to measure the reach of this additional effort.

As we step into an era of billions of devices empowering humans further, it is crucial that this system of systems is defect free especially when it touches safety critical part of our life. Negative testing is a potential way forward ensuring reliability of designs for such applications. As is always said – 

Better safe than sorry!

Sunday, March 4, 2018

Portable Stimulus : redefining verification play field yet again!

In the last 3+ decades, verification has come a long way! Right from quick testing by designers to dedicated verification teams moving from directed testing to constrained random and adding elements of formal apps at times, it has been an eventful journey! Standardization of UVM enabled a common framework with which the fraternity marched forward in sync with each other. Horizontal reuse viz. at the IP level experienced maximum benefits of UVM while vertical resume viz. from IP to SoC level observed limited returns. Apart from the methodology, verification has also proliferated beyond simulation or emulation into virtual prototyping, FPGA validation, post silicon functional validation & HW SW co-verification. Today, the reuse aspects are not limited from IP to SoC or across projects but between platforms too. It is extremely important to realize reuse of efforts at any level across different vehicles enabling first silicon success. The challenge however is that each of these vehicles involve multiple stakeholders like architects (Chip , SW, system), SystemC modelling engineers, RTL designers, verification engineers, prototyping experts, post silicon debuggers and SW developers, each defining & driving the stages of SoC design cycle. Different goals focusing on a specific stage, different approaches in solving these problems and different means of representing solutions has made the task of reuse across the platforms – a convoluted puzzle!!!

To solve this problem, Accellera initiated a task force called Portable Stimulus Working Group (PSWG) that reviewed the concern & potential solutions. After long & regular sessions of intense activity in last couple of years, the group has come up with a proposal in form of a standard.  Beta release of the preliminary version of the Portable Test and Stimulus Standard is now opened for public review.

The basis of the solution relies upon taking the stimulus definition across platforms to an abstraction layer where the focus is on what is needed instead of how it shall be implemented? The idea is to understand & represent the action/outcome i.e. the behavior of the DUT when the test runs. While representing these actions, the focus would be on what would be the inputs and outputs, what resources are required in the DUT, and their relationship with each other? The how part i.e. the implementation will be left to a hidden layer (read EDA tool) to generate the required stimulus for the target platform based on the scenario definition. The actions referred above are all declarative and not procedural or executable by themselves. A set of these static actions can be used to construct a scenario, analyzed for coverage to determine the paths to be traversed & dumped into a test format using the hidden layer.  

To represent these actions, the PSWG has proposed 2 formats - Domain Specific Language (DSL) that is close to System Verilog and a restricted C++ library. Both these formats have equivalent semantics that are completely interchangeable such that for each line in the DSL there is an exactly equivalent C++ library entry. If one defines the actions of an IP in DSL and another IP in C++ library, both can be read together to generate a SoC level scenario for the target platform.

While the road of moving from developing each testcase to a testbench that generates tests has been long, it’s time to take another step in the direction of standardizing the stimuli! This would feed the testbenches for IP/SoC verification & be reused by other workhorses of verification & validation in the SoC design cycle. Remember, reuse is one of the keys to keep up with Moore's law!!!

The public review period for this proposal is open until Friday, March 30, 2018. Download & review NOW!!!

Sunday, February 18, 2018

Moana of Verification!!!

Dear Readers!!!! Welcome back!!!

During this lull period of sharing thoughts, I realized that even blogging faces the same dilemma of verification on “How much is enough”. Finally, as a verification engineer should think, I decided to continue as much as I can with the hope to improve blogging frequency than before – wish there was  Moore’s law for bloggers too 😊!!! Since this is the first one of this year (Happy New year folks!!!) & by this time of the year the intent, action and discussions on new year resolutions would have died down mostly, let’s start from there.  While speaking to budding DV engineers on their new year resolutions around verification, I discovered that somehow focus on the end goal is missing & they seem to be trending into all directions. Reason? Well! Possibly many –
- The never ending gap between industry expectations & Academia.
- Missing core elements in the Job description of a verification engineers.
- Overwhelming solutions that enable verification….. etc.

Still confused on what I mean? Let me explain!

When I started my career as a verification engineer with legacy directed verification approaches, all I learnt was that, to be successful you need to have - a Nose for Bugs! In a way, that was also because one needed to maximize returns from each test so, you handcraft each one to really mine bugs. With rising silicon complexity, verification domain has been experiencing consistent advancements enabling us verify designs faster & better. During this shift, the expectations from verification engineers also kept changing i.e. demanding experience on new flow, language or methodology. The rise of SV & UVM further accelerated this shift giving a taste of elaborate & sometimes exotic code development opportunities for the DV engineers. While this continued, reuse gained momentum on the design & eventually on verification too. Due to this the code development gave way to reuse & with latest verification flow/methodologies, the verification engineers started spending more time on derivative designs that demand debug capabilities over development. 

Coming back to our budding engineers discussion, learning a new flow/methodology would end up having expectations on development work which may not really be needed always. This trend has often lead to the confusion of multiple directions where the engineer ends up settling on the means losing focus on the end goal.  As a DV engineer, our goal is to find bugs! Approaches like Directed/Constrained Random/Formal or languages, methodologies & platforms like simulator/emulator etc. are all means to hunt bugs. While expertise in many or all of these are important and occasionally may even lead to a career, the expectations from verification engineer is really to catch bugs! 

How does this relate to the topic of the blog?

Well! Moana is a film on the story of a girl named Moana, daughter of a chief of a Polynesian village. She is chosen by the ocean to reunite a mystical relic with a goddess. When a blight strikes her island, Moana sets sail in search of Maui, a legendary shapeshifting demigod, in the hope of returning the heart of Te Fiti and saving her people. In this journey of hers, she discovers that her tribe were ‘voyagers’ who have forgotten their virtue and settled as villagers on an island which would die down soon. She not only saves the island & her people but leads them back to their original self – a journey which is more exciting & enriching!

Similarly, UVM, formal apps and emulation etc. are all means to find bugs in your verification journey. Don’t just settle for the means which might be short-lived sometimes but shoot for the end goal & be the Moana of Verification!!! A worthy resolution to pursue 😊!!!    

What was your resolution on verification on this New Year???

Sunday, September 10, 2017

Quick chat with Vishal Dhupar : Keynote speaker DVCon India 2017

Vishal Dhupar
Imagine learning how to ride a bicycle! You learn to balance - pedal - ride on a straight line - turn - ride in busy streets - All set!!! It takes step by step learning & then if you are offered a different bicycle you would try to apply the “truths” you discovered in your earlier learning process & quickly pick up the new one too. Our machines so far perform the tasks they are programmed for and as obedient followers carry out the required job. However, the new wave of technology is striving to make the machines more intelligent, to not only seek but offer assistance, to make our decision making better, help an ageing population store & retrieve memories that fade and much more!!! Sounds interesting? Conniving? …???

Vishal Dhupar, Managing Director – Asia South at Nvidia would be discussing Re-Emergence Of Artificial Intelligence Based On Deep Learning Algorithm as part of the invited keynote on Day 1 DVCon India 2017. Passionate about the subject, Vishal shares the background & what lies ahead for us in the domain of AI & Deep Learning. Extremely useful from beginners to practitioners!!!

Vishal your keynote focusses on AI & Deep learning – intricate & interesting topic. Tell us more about it?

Curiously, the lack of a precise, universally accepted definition of AI probably has helped the field to grow, blossom, and advance at an ever-accelerating pace. Claims about the promise and peril of artificial intelligence are abundant, and growing.

Several factors have fueled the AI revolution which will be the premise of my talk. Touching upon how machine learning is maturing, and further being propelled dramatically forward by deep learning, a form of adaptive artificial neural networks. This leap in the performance of information processing algorithms has been accompanied by significant progress in hardware and software systems technology. Characterizing AI depends on the credit one is willing to give synthesized software and hardware for functioning appropriately and with foresight. I will be touching upon a few examples of AI advancements.

How do we differentiate between machine learning, artificial intelligence & deep learning?

Machine learning, deep learning, and artificial intelligence all have relatively specific meanings, but are often broadly used to refer to any sort of modern, big-data related processing approach. You can think of deep learning, machine learning and artificial intelligence as a set of concentric circles nested within each other, beginning with the smallest and working out. Deep learning is a subset of machine learning, which is a subset of AI. When applied to a problem, each of these would take a slightly different approach and hence a delta in the outcome.

Artificial Intelligence is the broad umbrella term for attempting to make computers think the way humans think, be able to simulate the kinds of things that humans do and ultimately to solve problems in a better and faster way than we do. Then, machine learning refers to any type of computer program that can “learn” by itself without having to be explicitly programmed by a human. Deep learning is one of many approaches to machine learning. Other approaches include decision tree learning, inductive logic programming, clustering, reinforcement learning, and Bayesian networks. Deep learning was inspired by the structure and function of the brain, namely the interconnecting of many neurons.

Some of the discussions on deep learning are intriguing. Does it lead to machines taking over jobs?

Machines are getting smarter because we’re getting better at building them. And we’re getting better at it, in part, because we are smarter about the ways in which our own brains function.

Despite the massive potential of AI systems, they are still far from solving many kinds of tasks that people are good at, like tasks involving hand-eye coordination or manual dexterity; most skilled trades, crafts and artisan- ship remain well beyond the capabilities of AI systems. The same is true for tasks that are not well-defined, and that require creativity, innovation, inventiveness, compassion or empathy. However, repetitive tasks involving mental labor stand to be automated, much as repetitive tasks involving manual labor have been for generations.

Let me give you an example your calculator is smarter than you are in arithmetic already; your GPS is smarter than you are in spatial navigation; Google, Bing, are smarter than you are in long-term memory. And we're going to take, again, these kinds of different types of thinking and we'll put them into, like, a car. The reason why we want to put them in a car so the car drives, is because it's not driving like a human. It's not thinking like us. That's the whole feature of it. It's not being distracted, it's not worrying about whether it left the stove on, or whether it should have majored in finance. It's just driving.

What are the domains that you see would see faster adoption & benefits of these techniques?

In healthcare, deep learning is expected to extend its roots into medical imaging, translational bioinformatics, public health policy development using inputs from EHRs and beyond. There is rapid improvements in computational power, fast data storage and parallelization have contributed to the rapid uptake of deep learning in addition to its predictive power and ability to generate automatically optimized high-level features and semantic interpretation from the input data.

Seems like the ASIC design flow/process can be equally benefited from these techniques. Your views on it?

Deep Learning in its elements is an optimization problem. Its application in any work flow or design process where there is scope for optimization carries enormous benefits. With respect to the design, fab and bring up of ICs, deep learning helps with inspection of defects, determination of voltage and current parameters, and so. In fact, at NVIDIA we carry out rigorous scientific research in these areas. I believe as we unlock more methods of unsupervised learning, we’ll discover and explore many more possibilities of efficient design where we don’t entirely depend of large volumes of labelled data which hard to get in such a complex practice.

What are the error rates in execution we can expect with deep learning? Can we rely on machines for life critical applications?

Deep learning will certainly out-perform us in few specific tasks with very low error rates. For example, classification of images is task where models can be far accurate than mortals. Consider the case of language translation, today machines are capable of such efficient and economic multi-lingual translation that it wouldn’t just be possible for a person. [Recently MSFT’s speech recognition systems achieved a word error rate of 5.1%on par with humans] While we look into health care where life critical decisions are made, deep learning can be used to improve accuracy, speed and scale in solving problems like screening, tumor segmentation, etc. and not necessarily declaring a person alive or otherwise!

In all the instance we just saw, state-of-art capabilities are developed in very specific and highly verticalized applications. Machine are smarter than us in these applications but nowhere close to our general intelligence in piecing these inputs together to make logical conclusions. From a pure systems and software standpoint, we will need guard rails, i.e. fail-safe heuristics that backup a model when it operates outside the boundaries to keep the fault tolerance at bay.  

This is the 4th edition of DVCon in India. What are your expectations from the conference?

While the 20th century is marked by the rise and dominance of the United States, the next 100 years are being dubbed the Asian Century by many prognosticators. No country is driving this tectonic shift more than India with its tech talent. NVIDIA is a world leader in artificial intelligence technologies and is doing significant work to train the next generation of deep learning practitioners. Earlier this year we announced our plans to train 100,000 developers in FY18 in deep-learning skills. We are working across academia and the startup community to conduct trainings in deep learning. I’m keen to understand the enthusiasm of the attendees in these areas and how NVIDIA can provide a bigger platform and bring the AI researchers and scientists community together. 

Thank you Vishal!

Join us on Day 1 (Sep 14) of DVCon India 2017 at Leela Palace, Bangalore to attend this keynote and other exciting topics!

Disclaimer: "The postings on this blog are my own and not necessarily reflect the view of Aricent"

Sunday, August 27, 2017

Quick chat with Ravi Subramanian : Keynote speaker DVCon India 2017

Dr. Ravi Subramanian
For many decades, the semiconductor industry followed Moore’s law, transforming what we called as a discrete chip carrying a function on silicon into a small IP inside the SoC on silicon today. As we continue to debate beyond Moore, more than Moore or stagnation of this law and step in the world of IoT, we realize that the system is no more only a single SoC, but instead, it is a conglomeration of multiple tiny & large systems working in tandem producing interesting use cases & enhancing user experience. But are we as the verification engineering workforce ready with the required skills along with the right arsenal of tools and efficient workhorses to ride through this new challenge?

Dr. Ravi Subramanian, Vice president and General manager of Mentor’s IC Verification Solutions Division shares a holistic view on this subject in his opening keynote on Day 2 at DVCon India 2017. The talk titled Innovations in Computing, Networking, and Communications: Driving the Next Big Wave in Verification, dives into convergence of different technologies and its impact on verification. A quick chat with Ravi, revealed the excitement that we all can look forward to in his talk as well as the future that lies ahead for all of us. Read on!!!

Ravi your keynote focusses on drivers to the next big wave in verification. Tell us more about it?

Yes, my talk will focus on the amazing innovations our industry is developing with respect to computing, networking, and communications. These include the changing nature of computing, the dramatic changes in networking and storage, and the disruptive effect of new broadband communications. Yet, the next big wave in design is actually the convergence of these technologies, which is driving today’s internet-of-things and autonomous systems revolution. A common theme across these emerging systems is the need for low power, security, and safety—whether you are talking about devices on the edge or high-availability systems in the cloud. These new challenges have opened innovation opportunities for us to rethink the way we approach verification

IoT is driving the convergence of different technologies. How would it affect the way we verify the systems today?

To answer your question, I first want to step back in time to provide a framework for today’s challenges. In the 1990’s the concept of separation of concerns was introduced into engineering. Essentially, the idea is that verification would become more productive if we focused on verifying orthogonal concerns or requirements of the design separately versus trying to verify multiple concerns combined. For example, during this period of time, we learned that it is more efficient to verify functional concerns and physical concerns in separate simulation runs. This approach to verification worked well up to about 10 years ago. The emergence of mobile devices introduced new low-power requirements that made it difficult to separate concerns. For example, today we see that physical concerns (such as low power management) now can directly affect functional behavior of a device. Hence, these concerns need to be verified together. Bringing together physical, electrical, and functional has become mandatory.

The key point is that convergence of computing, networking, and communication, which is driving IoT, has introduced new layers of verification requirements that did not exist years ago, and the interaction of these requirements has had a profound effect on the way we must verify systems today.

What are the solutions that the EDA industry is driving to enable this next big wave in verification?

One contributing factor to growing verification complexity is the emergence of new layers of verification requirements, as I previously mentioned. For example, beyond the traditional functional domain, we have added clock domains, power domains, mixed-signal domains, security domains, safety requirements, software, and then obviously, overall performance requirements. Hence, we see the next big wave in verification on multiple fronts:

Continuing introductions of focused solutions optimized for specific verification concerns. Examples of these focused solutions include: formal apps focused on  verifying security features within a design or power apps used to provide complete RTL power exploration and accurate gate-level power analysis within emulation.
Emerging system-level analysis solutions, which provide new metrics and insight into the fully integrated SoC. This becomes essential for system-level performance analysis. The IoT SoC, for example, is a different beast than today’s state-of-the art networking SoC.
Greater convergence across multiple verification engines (e.g., simulation, emulation, and FPGA prototyping), which will improve productivity. The new Accellera Portable Stimulus standard will help facilitate this convergence and foster the introduction of new verification solutions.
Q4: Do you see domain specific solutions like automotive or machine learning etc. getting enabled for verification?

Yes, in fact there are multiple opportunities to leverage big data analytics to solve many system-level analysis problems. Machine learning is only one approach used today for big data analytics; however, there are others. Now, concerning domain-specific solutions in the automotive space, formal technology is being leveraged to improve productivity related to safety fault analysis.

Do you expect all workhorses (Simulation, Emulation & Formal) playing a critical role in verifying these new converged system level designs?

Obviously, this depends on the design. A project developing sensors for an IoT edge solution has different verification requirements than a project developing an automotive SoC containing multiple CPU and GPU cores, a coherent fabric, and multiple complex interfaces. Nonetheless, with increased design integration, multiple verification engines are required today that address the growing volume of verification requirements.

This is the 4th edition of DVCon in India. What are your expectations from the conference?

DVCon, in general, is recognized as the premier conference on the application of languages, tools, methodologies and standards for the design and verification of electronic systems and integrated circuits. And DVCon India is no exception, which has continued to grow in both attendance and exhibitor participation. I expect DVCon 2017 will continue to deliver high-quality technical content and provide valuable networking opportunities for its attendees. It is the premier venue to share state-of-the-art developments and connect the creative minds working on these developments.

Thank you Ravi!

Join us on Day 2 (Sep 15) of DVCon India 2017 at Leela Palace, Bangalore to attend this keynote and other exciting topics.

Disclaimer: “The postings on this blog are my own and not necessarily reflect the views of Aricent”

Sunday, August 20, 2017

Quick chat with Apurva Kalia : Keynote speaker DVCon India 2017

Apurva Kalia
The advancements in semiconductor industry starting picking up with the rise in performance of processors driving the computer industry. Next, the mobile segment opened floodgates when the PC market stagnated & then low power with smaller dimensions on top of performance drove the innovation in silicon implementation. The industry today is at cross roads once again awaiting the next big thing. Automotive is one of the key areas to get the ball rolling yet again. But then, each domain has its characteristics that needs to be aligned to!

Apurva Kalia, Vice President of R&D focusing on Automotive solutions at Cadence picks on an interesting topic for his DV track keynote on Day 1 at DVCon India 2017. With the auto industry shifting gears into autonomous cars, the question worth asking is – Would you send your child to school in an autonomous car? Yes, that’s the theme of Apurva’s keynote and here’s a sneak peek on this topic.

Apurva your keynote focusses on ‘autonomous cars’ – the talk of the town these days. Tell us more about it?

Well, there is major inflection point coming up in automotive electronics. We all know that Moore’s Law driven advances in cost per transistor and capacity have been holding up for many years. Complex chips are now possible within a cost factor that was not possible earlier. Moreover advances in algorithms, especially Machine Learning, now enables much more complex processing, especially vision based processing, to be done in real time. Both these trends coming together with advances in sensor technology has enabled systems to be created which can detect their environment quite accurately and in real time. This is the basis of autonomous driving. Also, as we know, every few years the semiconductor industry is looking for the next big trend which will drive the fab capacity. The above factors are pushing autonomous driving to be the talk of the town.

Security & Safety are emerging areas resulting from this topic. How does this change the way we verify our designs?

As I described above, with autonomous driving really taking off, these systems are becoming mission critical for the automobile. This means that the system needs to be safe and secure. It is inconceivable for a car to stop working at 80 kmph on a highway! Also, with the car needed to be connected to other cars and even to infrastructure and internet, this opens the system to attacks and makes it vulnerable. Therefore, these systems needs to make safe and secure to ensure safety and security of the automobile.

What are the solutions that the EDA industry is driving to enable ISO 26262 requirements from process & product perspective?

ISO26262 is the main standard that defines the safety requirements for automobiles. It is a very comprehensive standard which places requirements on all automotive systems. In fact edition 2 of the standard – coming out in Jan 2018 – will focus specially on semiconductors. Given the excitement around automotive electronics and autonomous systems, EDA industry needs to retool rapidly to address this need. Ensuring safety in these designs requires additional design and verification flows, methodologies and tool changes. The EDA industry needs to step up to define and create these flows, methodologies and tools required.

What are your views on the couple of accidents that happened in the US with autonomous cars? What could have been done better?

We are at early stages of this technology. Unfortunately as with any new technology, technology will take time to stabilize. In the meantime, during this stabilization time, unfortunate things like these accidents could happen. Organizations and individuals who are early adopters of these technologies take these risks, but they also contribute in a big way for advancement of these technologies. However, with the proper use of tools, implementation of standards, and focus on new solutions, we can avoid these kind of accidents.

How do you observe the adoption of autonomous cars across the globe & in India?

Autonomous cars are here to stay. They are solving real problems in real environments. We already have examples of autonomous cars on real roads – driving very safely. In fact, there are statistics which show that autonomous cars will actually cut down on accidents and fatalities – the most of which are caused by human error. Last year, I saw an engineering college in Delhi demonstrate an autonomous vehicle in Govindpuri – one of the most congested areas of Delhi. So this technology is real and works. I think it is just a matter of a few years when we will see this mainstream.

Do you see all workhorses (Simulation, Emulation & Formal) playing a critical role in realizing Auto grade designs?

Yes – all current EDA technologies – not just verification technologies, but even implementation technologies – need to be upgraded to support safety and security design and verification. All engines will need enhancements and special features to support these new requirements and flows.

This is the 4th edition of DVCon in India. What are your expectations from the conference?

I have seen DVCon India grow from humble beginnings to an excellent conference today. I think this conference provides a very good platform to share and discuss new trends in design and verification. I look forward to stimulating conversations on new flows and technologies. This conference attracts many design companies and all EDA vendors in India – what better assemblage of the right people for these discussions.

Thank you Apurva!

Join us on Day 1 (Sep 14) of DVCon India 2017 at Leela Palace, Bangalore to attend this keynote and other exciting topics.

Disclaimer: “The postings on this blog are my own and not necessarily reflect the views of Aricent”

Monday, March 27, 2017

Ni Hao China? says DVCon

Miniaturization of devices is marching into the range where the acceleration may not be contained in one dimension anymore. This is leading to growth in 2D & 3D for packing more functions on a given silicon area. One of the key factors that has enabled this race so far is also the globalization of workforce. Whether the reasons were tapping the talent world-wide or ensuring the work continues round the clock or reduce cost of development. With the tech world turning into a global village, there was a need felt to ensure different age groups, different cultures & different working styles, talk a common language. This has been the prime motive of Accellera working groups getting together from across the world to define standards and methodologies and providing a common ground for everyone to contribute. While rolling out standards is a key outcome of this consortium, encouraging the adoption & ensuring correct application of these standards is equally important. This is one of the prime reasons that the flagship conference DVCon was extended beyond geographies (DVCon goes GLOBAL!) a few years back when India & Europe embraced it with an overwhelming response. This year the 29th edition of DVCon US witnessed 1000+ participants  over a 4-day conference continuing the momentum year after year. However, this caravan would see another stopover before it reaches India in September this year. YES!!! DVCon would be debuting in the Mandarin land this year - DVCon China 2017!!!

If you have any doubts on why China? Let’s review a few interesting pointers from the latest report by PWC titled China’s impact on the semiconductor industry : 2016update

  • China’s semiconductor consumption growth continued to far exceed worldwide semiconductor market growth for the 5th consecutive year in 2015 reaching a new record of 58.5% of the global market. China’s semiconductor industry has grown at an equal or greater rate than its semiconductor market consumption for eight of the past ten years. In 2015, China’s semiconductor industry grew by 15.5% to a record US$89.3bn.
  • China’s IC industry grew by 17.1% in 2015 despite a decline in the global IC market. Since 2010 China’s IC industry revenues have more than doubled, growing 170%. Starting from a very small US$2.2bn base in 2000, China’s IC industry has grown much faster than the worldwide IC market for every subsequent year except 2010 with revenue touching 2015 to US$57.5bn.
  • Integrated circuit (IC) design continues to be the fastest growing segment of China’s semiconductor industry. During the ten years from 2005 through 2015 China’s IC design (fabless) industry has grown at a 30.1% compound annual growth rate (CAGR) from US$1.52bn to just over US$21bn in 2015.
  • The China Center of Information Industry Development (CCID) reports that the number of China’s IC design enterprises increased from 681 in 2014 to 715 by the end of 2015 with the total number of employees in China’s IC design totaling to about 155,000.
These pointers clearly confirm that the semiconductor industry is growing in China at an unparalleled speed and hosting a conference to bring in the stakeholders together would further stimulate the development process. Clearly a thoughtful decision by Accellera!

Coming back to the details of the event, the 1st edition of the Design and Verification Conference and ExhibitionChina is planned for 19, April 2017 at the Parkyard Hotel, Shanghai. DVCon China provides an excellent platform to bring together the global semiconductor industry in general & the China semiconductor industry in particular, along with academia and international standards development organizations. The 1 fullday event is completely packed with an assortment of keynotes from eminent speakers, tutorials from the gurus, papers & posters from practitioners and avenues for networking, learning opportunities, and exciting exhibits with different offerings. Along with experts from China there is an active participation from universities like Tsinghua and Fudan as part of the DVCon China steering and program committees. The day starts with keynote from Dr. Wally Rhines - CEO Mentor Graphics on the topic Design Verification:Challenging Yesterday, Today and Tomorrow while the event concludes with another interesting talk on What's Next in Verification from Yong Fu – Group Director, Synopsys. 

Leaders from the local industry with extended support from experts across the globe have put together a fantastic program for you to actively participate in person and be part of this enriching experience.

Reiterating the words of Benjamin Franklin that truly exhibit the spirits of DVCon–

Tell me and I forget.
Teach me and I remember.
Involve me and I learn.

 Get involved NOW!!! Registrations open with early bird discounts - here


Disclaimer: "The postings on this are my own and not necessarily reflect the views of Aricent".

Friday, September 9, 2016

Quick chat with Alok Jain : Keynote speaker, DVCon India 2016

Alok Jain
All of us have heard the story of a woodcutter and the importance of the quote “Sharpen your axe”. It applies well to everything we do including verification. Two decades back, the focus of a verification engineer was predominantly on “What to Verify”. As complexity grew “How to Verify” became equally important. To enable this, EDA teams rolled out multiple technologies & methodologies. As we try to assimilate & integrate these flows amidst first time silicon & cost pressure, it is important for us to sharpen our axe through continuous learning, applying the right tool for the right job and applying it effectively.

Alok Jain, Senior Group Director in the Advanced Verification Division at Cadence would be discussing on similar lines as part of his DV track keynote on Day 1 at DVCon India 2016. With 20+ years of industry experience, Alok leads the Advanced Verification Division at Cadence India. Having associated with different technologies around verification in the past 2 decades, Alok candidly shared his views on the challenges beyond complexity that verification teams need to focus on. Here is a curtain raiser for his talk "Verification of complex SoCs" 

Alok your keynote topic focuses on challenges in verification beyond the complexity resulting from Moore’s law. Tell us more about it?

The keynote is going to focus on challenges and potential solution for verification of complex SoCs. Verifying a complex SoC consisting of tens of embedded cores and hundreds of IPs is a major challenge in the industry today. One of the big challenges is performance and capacity. Given the size and complexity of modern SoCs, tests can run for 18-24 hours or even more. One has to figure out how to get the best verification throughput. Another challenge is generation of test benches and tests. The test benches have to be developed in a way which can achieve good performance in both simulation and hardware acceleration. Tests have to be created that stress the SoC under the application use cases, low power scenarios, and multi-core coherency scenarios. The tests have to be re-usable across pre-silicon and post-silicon verification and validation platforms. Yet another challenge is coverage. One has to measure verification coverage across formal, simulation, and acceleration platforms at the SoC level to know when you are done. The final challenge is how to effectively debug across RTL, test bench, and embedded software on multiple verification platforms.

In the last decade, advancements in verification was focused primarily on unifying HVL(s) & methodologies. What changes do you foresee in verification flows ‘Beyond UVM’?

UVM is very well suited for IP, Sub-system and some specific aspects of SoC verification. However, UVM is not the best approach for general SoC verification. UVM is essentially developed for “bottom-up” verification where the focus is on trying to exhaustively verify IP/sub-systems. SoCs require a more “top-down” verification where the focus is on stressing the SoC under important application use cases. There is a need to reuse SoC content across simulation, emulation, FPGA and post-silicon. UVM is optimized for simulation and is too slow and heavy for high speed platforms. Finally, there is a need to drive software stimulus on CPUs in coordination with hardware interfaces. It is difficult in UVM to drive and control software and hardware interfaces. All this is asking us to explore options beyond UVM. The keynote will cover some more insights into options beyond UVM.

The rise of IoT is stretching the design demands to far ends i.e. server class vs edge node devices. How do you see verification flows catering to these demands?

Several of the requirements for IoT verification are similar to the ones for complex SoCs. But then there are some unique additional requirements from the IoT world. The first is simply the cost of verification. For complex SoCs, the cost of verification has been steadily rising. For IoT applications, one has to consider alternative methods and flows that can reduce the cost. One option is to use some form of a correct by construction approach where the design is specifically done in a way to enable a simpler form of verification. Another approach is to put much more emphasis on reuse. This includes horizontal reuse which is portability across multiple platforms and vertical reuse which is reuse from IP to sub-system to SoC. Another requirement is verification throughput for design with considerably more analog, mixed signal and low power content. Finally, one has to devise verification techniques and flows that can cater to the security and safety requirements of modern IoT applications.

Formal took a while to become mainstream. The rise of Apps in Formal seems to have accelerated this adoption. What’s your view on this?

Yes, I do agree that Apps has considerably accelerated the pace of adoption of formal. Traditionally, formal tools have been developed and used by formal PhDs and experts. The main charter and motivation of these experts was to solve the coolest and hardest problems in formal verification. It was only after some time that both sides (developers and users) started realizing that formal can be used in a much more practical and usable way by engineers to solve specific problems. This lead to the development of various formal apps which greatly enabled the mainstream usage of formal.

This is the 3rd edition of DVCon India. What are your expectations from the conference?

I am expecting to attend keynotes, technical papers and panel discussions that give me an understanding of some the latest work in the domain of design and verification of IPs, sub-systems and SoCs. In addition, I am looking forward to the opportunity to network with some of my peers from the industry and academia.

Thank you Alok!

Come join us in this exciting journey to contribute, collaborate, connect & celebrate @ DVCon India 2016!

Disclaimer: “The postings on this blog are my own and not necessarily reflect the views of Aricent”

Saturday, September 3, 2016

Quick chat with Sushil : Keynote speaker, DVCon India 2016

Sushil Gupta
A very famous urdu verse that translates  translates to “When I started I was alone, slowly others joined and a caravan formed” truly describes the plethora of challenges in SoC verification that continues to abound as the design complexity marches north. It started with growing logic on the silicon and moved to performance before power took over. While we still juggle up to handle the PPA implications, time to market pressure with cost effective secure customized solutions further add enough spice to the problem.

Sushil Gupta, Group Director in the Verification group at Synopsys covers these problems & potential solutions in his keynote titled “Today’s SoC Verification Challenges: Mobile and Beyond” on Day 2 of DVCon India 2016. Sushil joined Synopsys in 2015 as part of acquisition of Atrenta. He has 30 years of industry experience which spans various roles in engineering management and leadership in EDA and VLSI Design companies. Here is a quick excerpt of the conversation with Sushil around this topic –

Sushil your keynote topic focuses on challenges in verification associated with the next generation of SoCs. Tell us more about it?

We have seen the chip design industry shift its focus from computers and networking into System on Chips (SoC) for mobility – smartphones, tablets, and other consumer devices. The next wave of SoCs go beyond mobility into IoT, automotive, robotics, etc. These SoCs integrate hundreds of functions into a single chip and a complete software stack with drivers, operating system, etc.. The result is 10X increase in verification complexity in continually shrinking market windows. My talk focuses on these challenges and how verification solutions must scale to address them effectively.

Reuse of IP/Subsystems is the key trend with SoCs today. Do you think that reuse from third party add to challenges in verification? If yes, how?

IP/sub-system reuse (both third party and in-house) helps accelerate the integration of multiple functions into a single chip. However, these IP/sub-systems can come from multiple sources with heterogeneous design and verification flows. The resulting SoCs are extremely complex with  millions of lines of RTL and testbench, protocols, assertions, clock and power domains, and billions of cycles of OS boot.

Do you think progress in verification methodologies & flows have reached to a point where consolidation is key to allow verification engineer use the best of each? Any specific trends that you would like to highlight on this?

Integrated verification platforms are key to verification convergence. Verification now extends beyond functional verification into low power verification, debug automation, static  and formal verification, early software bring-up and emerging challenges with safety, security and privacy. This requires not only best-in-class verification tools and engines, but also native integrations between the tools to enable seamless transitions and faster convergence.

Sushil you have had a significant stint with formal at Atrenta. What are your thoughts on adoption of Formal coming to mainstream? How does the trend looks moving forward?

Formal is fast becoming mainstream because it can catch bugs that are otherwise very difficult to detect. Advancements in performance, debug and capacity of formal verification tools has enabled formal to become an integral part of a comprehensive SoC verification flow. The emergence of formal ‘Apps’ for clock and reset domains, low power, connectivity, sequential equivalence, coverage exclusions, etc. has enabled a broad range of design and verification engineers to benefit from formal verification without the need to be a formal “expert”.   

This is the 3rd edition of DVCon India. What are your expectations from the conference?

Speaking from my own experience having started my career with TI India in 1986, India has a very rich design and verification expertise. I hope to learn about the latest challenges and innovations in verification and look forward to working with our customers and partners on new breakthroughs.

Thank you Sushil!

Join us on Day 2 (Sept 16) of DVCon India 2016  at Leela Palace, Bangalore to attend this keynote and other exciting topics.

Disclaimer: “The postings on this blog are my own and not necessarily reflect the views of Aricent”

Saturday, August 27, 2016

Quick chat with Wally : Keynote speaker, DVCon India 2016

Walden C. Rhines
It takes a village to raise a child! Correlating it with the growth of an engineer, YES! it does require Contribution from many & Collaboration with many. While our respective teams play the role of a family, the growth is accelerated when we Connect beyond these boundaries. DVCon India is one such platform to enable all of these for Design, verification & ESL community. The 3rd edition of DVCon India is planned on September 15-16 at Leela Palace, Bangalore.

The opening keynote on Day 1 is from Walden C. Rhines, CEO & Chairman, Mentor Graphics. It is always a pleasure to hear his insights on the Semiconductor & EDA industry. This year, he picked up an interesting topic – “Design Verification: Challenging Yesterday, Today and Tomorrow”. While we all wait with excitement to hear him on Sept 15, Wally was kind enough to share his thoughts on some queries that came up after I read the brief about his keynote. Below is an unedited version of the dialogue for you.

Wally your keynote topic is an excellent start to the program discussing the challenges head on. Tell us more about it?

Our industry has done a remarkable job of addressing rising complexity in terms of both design and verification productivity. What’s changed recently in verification is the emergence of a new set of requirements beyond the traditional functional domain. For example, we have added clocking, power, performance, and software requirements on top of the traditional functional requirements; and each of these new requirements that must be verified. While a continual development of new standards and methodologies has enabled us to keep pace with rising complexity and be productive, we are seeing that requirements for security and safety are becoming more important and could ultimately pose challenges more daunting than those we have faced in the past.

In the last few years ESL adoption has improved a lot. Is it the demand to move at higher abstraction level or convergence of diverse tool sets into a meaningful flow that is driving it?

Actually, a little of both. Historically, our industry has addressed complexity by raising abstraction when possible. For example, designers now have the option of using C, SystemC, or C++ as a design entry language combined with high-level synthesis to dramatically shorten the design and verification cycle by producing correct-by-construction, error-free, power-optimized RTL.

Moving beyond high-level synthesis, we are seeing new ESL design methodologies emerge that allow engineers to perform design optimizations on today’s advanced designs more quickly, efficiently, and cost-effectively than with traditional RTL methodologies by prototyping, debugging, and analyzing complex systems before the RTL stage.  ESL establishes a predictable, productive design process that leads to first-pass success when designs have become too massive and complex for success at the RTL stage.

The rise of IoT is stretching the design demands to far ends i.e. server class vs edge node devices. How does the EDA community view this problem statement?

Successful development of today’s Internet of Things products involves the convergence of best practices for system design that have evolved over the past 30 years. However, these practices were historically narrowly focused on specific requirements and concerns within a system. Today’s IoT ecosystems combine electronics, software, sensors, and actuator; where all are interconnected through a hierarchy of various complex levels of networking. At the lowest level, the edge node as you referred to it, advanced power management is fundamental for the IoT solution to succeed, while at the highest-level within the ecosystem, performance is equally critical. Obviously, EDA solutions exist today to design and verify each of these concerns within the IoT ecosystem. Yet more productivity can be achieved with more convergence of these solutions when possible.  For example, there is a need today to eliminate the development of multiple silos of verification environments that have traditionally existed across various verification engines—such as simulation, emulation, prototyping, and even real silicon used during post-silicon validation. In fact, work has begun with Accellera to develop a Portable Stimulus standard which will allow engineers to specify the verification intent once in terms of stimulus and checkers, which then can be retargeted though automation for a diverse set of verification engines.

Wally you seem to love India a lot! We see frequent references from you about the growing contribution of India to the global semiconductor community. Any specific trends that you would like to highlight?

Perhaps one of the most striking findings from our 2016 Wilson Research Group Functional Verification Study is how India is leading the world in terms of verification maturity. We can measure this phenomenon by looking at India’s adoption of  System Verilog and UVM compared to the rest of the world, as well as India’s adoption of various advanced functional verification techniques, such as constrained-random simulation, functional-coverage, and assertion-based techniques.

This is the 2nd time you would be delivering a keynote at DVCon India. What are your expectations from the conference?

I expect that the 2016 DVCon India will continue its outstanding success as a world-class conference, growing in both attendance and exhibitor participation, while delivering high-quality technical content and enlightening panel discussions.

Thank you Wally! We look forward to see you at DVCon India 2016.

Disclaimer: “The postings on this blog are my own and not necessarily reflect the views of Aricent”