Sunday, September 26, 2010

Living the PRESENT - the current decade!

The present decade witnessed the metamorphosis of verification domain from adoloscence to maturity. A lot of the initiatives from the last decade paid off well to scale verification along with the ASIC designs while a lot of new investments were made keeping the next decade in mind. Some verification features that made their mark in this decade include -

1. System Verilog - touted as a one stop solution for HDL+HVL, addressing the limitation of the designers using HDLs (Verilog/ VHDL) and the verification engineers debating on HVLs (e/Vera). An extension of Verilog 2005 and largely based on OpenVera language, System Verilog became a darling of everyone from the Semiconductors as well as the EDA companies.

2. Standardization of HVLs e & SV - System Verilog was adopted as IEEE Standard 1800-2005 and then merged with the Verilog IEEE 1394-2005, leading to IEEE Standard 1800-2009. 'e' language promoted by Verisity and bought by Cadence went ahead getting standardized as IEEE 1647-2006. 

3. CDV - Code coverage stagnated as a baseline for measuring verification progress & completeness. Functional coverage supported by the HVLs was able to put forward a different dimension and widely accepted. Assertion coverage though promising wasn't able to spread its wings wide enough, partly, since it was scenario focussed and partly because of ownership issues between design & verification teams. Even test planning evolved a lot with many tools now aiding in developing a robust test plan by keeping a track of architecture document and extending means for defining comprehensive coverage goals upfront.

4. Reusability - A jargon that still makes news every now & then. Design complexity jumping new heights and time to market panic lead to evolution of IP designs and reusability. With design, verification IPs also defined their market quite strongly. Methodologies (eRM & RVM) helped in packaging the verification environment so as to make it portable from module to chip level and between programs. SV evolution brought in OVM & VMM complementing eRM & RVM respectively. [Note - OVM is a mix of eRM & AVM]. Finally, this decade will commence with standardization of methodology - UVM.

5. AMS - The intricacies of Analog always kept it behind the digital world in terms advancements in process technologies or other methodologies. Product demands from various domains lead to single chip (packaging) and later single die solutions. Since analog & digital designers were always alien to each other these integrated designs demanded verification. AMS simulations addressed this space with various schemes like - Gate level representation of digital & transistor level representation of analog, Gate level or RTL representation of digital & behavioral modeling of the analog etc.

6. Formal verification - Directed verification opened gates to constrained random verification (CRV) where unforseen scenario generation was the focus.
Given time & resource limitations CRV couldn't reach to all possible points in the designs. Formal approach proposes to resolve these limitations. Slow advancement on the simulators limited the adoption of this methodology for most part of the decade.

7. Low power verification - Area and performance had been defining ASIC designs until power became an important measure. Innovative design techniques reduced power consumption with an overhead logic. EDA tools capable of verifying power aware designs - MVSIM & MVRC from Archpro (later acquired by Synopsys) and Cadence IUS & Conformal LP did quite well to address this issue. UPF & CPF emerged as two power formats that rushed to address representation of power aware designs. [UPF - IEEE 1801-2009].
 
8. Hardware accelerators - More gates, big designs, long simulation run time = bottleneck to tapeout in time. Next generation of hardware accelarators paved way for reducing the simulation turn around time. These boxes soon took shape of a complete platform for verification of the whole system and further advanced to help simulate some real time data into the designs before tapeout with much ease.

9. HW SW co-verification - With design focus shifting from the ASIC to SOC, system design & modelling became all the more important. Software testing became the next chokepoint for time to market. A well defined platform where software design & testing could start in parallel to the ASIC design came forefront. Better HW SW partioning, performance checks, system design issues etc all were well addressed with this platform.

10. Courses in verification - VLSI course became more prominent and adopted in almost all electrical & electronics courses. Late in the decade a need for focussed verification courses took centre stage. Many institutes delivering these courses addressed the need for a competent verification work force.

Next -
'Predictions for future - the next decade!'

Previous -
'Recap from the past - the last decade!'
 

Tuesday, September 14, 2010

Recap from the PAST - the last decade!

Verification has evolved a lot in the past 2 decades and there is more to come as we step in the next decade. This 3 part series lists out the highlights of the past, the present & predictions for the future.

Nineties had a crucial role in justifying verification to get a prominent berth in ASIC design cycles, ASIC schedules and ASIC teams. It was during this decade when verification commenced with full pace. Following are some milestones that helped achieve this. Some of them peaked & stagnated while others blossomed to scale even bigger in the following decade.

1. Standardization of HDLs and ownership of revised versions.
- VERILOG - IEEE 1364-1995 [Latest version 1364-2001, 1364-2005]
- VHDL - IEEE 1076-1987 [Latest version 1076-1993, 1076-2002]
- (OVI) Open Verilog International and VHDL International merged in 2000 to form Accellera.

2. The Simulator war.  Following are the ones that received wide acceptance -
- Verilog XL [Interpreter]
- VCS (Verilog compiled simulator) [Compiler]
- Modelsim

3. Directed verification - With low gate count, HDLs/C based verification was the softest path to tapeout. The test plans and test benches were primitive enough targeting only the features to be verified with no scalability & reusability.

4. Defined verification teams - With increasing design size (gate count) and  complexity there was a need to parallelize the effort of RTL with verification. Other factors like, having second pair of eyes to look into code and verification comprising 70% of asic schedule etc. ignited the look-out for dedicated verification teams to tame the bugs in the design.

5. Automation of verification infrastructure - The increasing complexity and no. of tests were a challenge to manage. Scripting took the front seat to automate the whole process of verification which includes, running tests in batch mode, checking for failures, regressions etc.  Typically every organization had a script called runsim as a initial step to get the flow working.

6. Constrained random verification - With design advancements poised to follow Moore's law directed verification saturated and there was a need for controlled aka constrained random stimuli to uncover unforseen bugs. C++ came up to rescue followed by hardware verification languages like Vera & e.

7. Code coverage - Increasing verification complexity lead to the basic but intricate question - 'are we done'? Covering the RTL code with the given set of stimuli has been one of the important milestone defining closure since then.

8. Gate level simulations - With equivalence checkers still stabilizing, setting up gate level simulations flow was crucial to ensure the synthesized netlist was sane enough to go for a tapeout.

9. Hardware accelarators - The concept of FPGA prototyping was replicated to develop boxes that could synthesize the design and run them 10x or faster to reduce the test case turn around from days to hours.

10. ASIC design as part of the curriculum was introduced at institutes in India offering Micro-electronics/VLSI as a subject in graduation and as a complete stream for post graduation. This helped source engineers to meet the demand for the semiconductor industry.

Tuesday, September 7, 2010

SNUG 2010, Bangalore

Although it's been a couple of months, I still thought of sharing my experiences from SNUG, one of the most touted conference in VLSI industry. SNUG 2010 @ Leela Palace Bangalore was witnessed by almost 2000+ engineers.

For me it was the first time I attended this event. Thanks to the recession that forced me to pack my baggages from Noida and move to Bangalore where most of the action is.

It started with the CEO Dr. Aart de Geus sharing vision of future from Synopsys perspective with a jam packed audience from the engineering community.

A few interesting messages from his keynote -
- Growth of semiconductor business = f(technology + state of economy) = Technomics.
- India & china slowly claiming stake with 6% & 9% growth during shrinking economy worldwide.
- Even though technology tried to pace up with Moore's law the ROI is failling behind.
 
He also listed technologies to watch out for in 2010 -
- Cloud computing
- Energy conservation
- Video applications
 
After his enlightening talk, the technical tracks picked up. Since I was keen on keeping my tryst with taming bugs I jumped into the verification track. It started off with summarizing future trends on verification and then went into core technical where Synopsys users shared their interesting experiences.
 
Interestingly, there was an EXPO planned in the evening with different partners from the VLSI ecosystem show casing their products & services - a new feature successfully added to SNUG India.
 
Next day kicked off with a keynote from Global Foundries followed by an interesting session on cloud computing and verification papers.

Overall the SNUG expereince was good. Got a chance to meet friends and old colleagues. On my way back after 2 days of conference the mood was in sync with the BAG (probably inspired by bollywood flick - 3 idiots) gifted to the SNUG attendees by Synopsys symbolizing ALL IS WELL!!!






What's in here?

Welcome to my blog which unveils the exciting world of verification in words!!!

sid'dha-karana aka Verification will explore the 'kal, aaj aur kal of verification' - literally translates to 'yesterday, today & tommorow of verification (context matters! the word 'kal' changes meaning with context of time).

This blog is primarily targeted to ASIC/SOC & related verification and will share -
past      - legacy stuff...
present  - insight into what's going around...
future    - some predictions and trends for future...

The hindi lingo above reflects my mother tongue (Hindi) and signifies that, the discussions though will cover verification irrespective of geography in general but will still have some focus on India in particular.

The breadth of the topics expected to be covered are -
- Verification basics
- Verification flow
- Verification languages & methodologies
- General about semiconductor industry

Apart from this I plan to spice it up with "Experiences", "Interview Questions" and ofcourse excerpts from discussions with the who's who from verification domain in our industry.

The above are guidelines to start off with. We can do a makeover as & when demanded, after all the only thing constant is change :)

Enjoy reading & continuing your experiments with BUG HUNTING!

Do drop in line of what you think about the blog to siddhakarana@gmail.com

Yours Truly,
Gaurav Jalan